1. Field of the Invention
The present invention is directed toward the field of synchronous circuits, and more particularly toward testing of synchronous circuits.
2. Art Background
Data communication systems transport data at a speed defined by a predetermined data rate. The speed of transmitting data in modern broadband communication systems has rapidly increased in recent years. Today, data rates as high as 40 gigabits per second (“Gbps”) are required for the OC-768 optical networking standard.
These data communication systems include basic synchronous circuits, such as latches, flip-flops, and constituent logic gates. To operate at high data rates, the synchronous circuits must also switch at high speeds (i.e., the synchronous circuits require a high bandwidth of operation). Thus, the high-speed synchronous circuits require the use of a high-speed clock with low jitter. Another requirement to effectively implement high-speed synchronous circuits is to minimize power dissipation.
To help meet these requirements, it is becoming increasingly more common to use inductive-capacitive (“LC”) tuned amplifiers as clock buffers. The LC tuned amplifiers, used to distribute clocks in the high-speed synchronous circuits, drive large capacitive loads on the clock line. These LC tuned amplifiers operate at high impedances within a narrow frequency range (i.e., a narrow clock data rate). For example, a phase lock loop (“PLL”) with an LC tuned voltage controlled oscillator may be used to generate the clock and an LC tuned amplifier may be used to buffer the clock.
Synchronous circuits typically include inputs to receive test or bypass clocks. In general, the bypass clocks are input to sections of the synchronous circuits to test the circuits. When debugging timing problems, it is desirable to set the bypass clock over a wide frequency range. In one application, the frequency or clock rate of the bypass clock is relatively low. For high-speed synchronous digital circuits, the frequency or clock rate of the bypass clock may be significantly lower than the clock rate of the device under normal operation. Unfortunately, the use of LC tuned amplifiers in these environments is limited because LC tuned amplifiers have a relatively narrow tuning range. Specifically, the LC tuned amplifiers only amplify over a limited frequency band due to the bandpass response of the tuned load. Thus, traditionally, LC tuned amplifiers preclude testing circuits over a wide frequency range.
To overcome frequency limitations at tuned nodes, an external clock may be injected into the integrated circuit chip through a bypass mode of operation. Typically, the clock is injected through a multiplexor (“MUX”) at the output of the PLL. FIG. 1 illustrates a prior art circuit used to implement a conventional clock bypass mode. As shown in FIG. 1, the conventional clock, fc, and a bypass clock, fb, are input to MUX 120. MUX 120 is controlled by a mode selection (i.e., selecting either the conventional clock or the bypass clock). The clock, output from MUX 120, is input to buffer 130. The buffer 130 drives a capacitive load, illustrated by capacitor 140, for input to a plurality of digital circuits (flip-flops 150, 152, 154 and 156).
As explained herein, it is desirable to provide a bypass clock to high-speed synchronous circuits without impeding the operation of the circuits. It is also desirable to provide a bypass clock to high-speed synchronous circuits with an LC clock buffer.